Multiple interleaved Analog-to-Digital (ADC) converters are widely used to increase the sampling rate of the conversion. In order to adjust the multiple ADC's so that they perform equivalently, a typical commercially available high-speed ADC has build-in adjustable controls for the DC offset, gain, and clock timing. In addition to the DC offset, gain, and clock timing differences between ADC's, the amplitude frequency response and the group delay frequency response of ADC's are also not identical. These differences might arise from differences in the frequency responses of the analog signal distributing circuitry or the analog front end of an ADC (e.g., input amplifier, track-and-hold circuit, etc.), which are difficult to eliminate given current design practices and process technology variations. It is therefore necessary to equalize the response characteristics of the different ADC's. One equalization strategy is to digitally equalize after each ADC. However, equalizing each ADC separately limits the bandwidth over which the equalization can be done; especially since an individual ADC is only 1/N of the overall bandwidth desired given N ADC's in a system. Another equalization strategy is to digitally equalize after the ADC streams have been combined. However, at this point the different ADC frequency responses and group delays are intermingled and cannot be removed by a simple equalizer. In addition, in some cases, the equalizer uses FFT transforms in order to equalize in the frequency domain, and significant computation delay and complexity is introduced into the signal processing. It would be beneficial to be able to equalize the interleaved digitizer samples at full bandwidth without suffering from the intermingled ADC responses.